| CFh |
Test CMOS
read/write functionality |
| C0h |
Early chipset
initialization: Disable shadow RAM, L2 cache
(socket 7 and below), program basic chipset registers |
| C1h |
Detect memory:
Auto detection of DRAM size, type and ECC, auto detection
of L2 cache (socket 7 and below) |
| C3h |
Expand compressed
BIOS code to DRAM |
| C5h |
Call chipset
hook to copy BIOS back to E000 & F000 shadow RAM |
| 01h |
Expand the
Xgroup codes located in physical memory address 1000:0 |
| 02h |
Reserved |
| 03h |
Initial Superio_Early_Init
switch |
| 04h |
Reserved |
| 05h |
Blank out
screen; Clear CMOS error flag |
| 06h |
Reserved |
| 07h |
Clear 8042
interface; Initialize 8042 self test |
| 08h |
Test special
keyboard controller for Winbond 977 series Super I/O
chips; Enable keyboard interface |
| 09h |
Reserved |
| 0Ah |
Disable PS/2
mouse interface (optional); Auto detect ports for keyboard
& mouse followed by a port & interface swap
(optional); Reset keyboard for Winbond 977 series Super
I/O chips |
| 0Bh |
Reserved |
| 0Ch |
Reserved |
| 0Dh |
Reserved |
| 0Eh |
Test F000h
segment shadow to see whether it is read/write capable
or not. If test fails, keep beeping the speaker |
| 0Fh |
Reserved |
| 10h |
Auto detect
flash type to load appropriate flash read/write codes
into the run time area in F000 for ESCD & DMI support |
| 11h |
Reserved |
| 12h |
Use walking
1's algorithm to check out interface in CMOS circuitry.
Also set real time clock power status and then check
for overrride |
| 13h |
Reserved |
| 14h |
Program chipset
default values into chipset. Chipset default values
are MODBINable by OEM customers |
| 15h |
Reserved |
| 16h |
Initial Early_Init_Onboard_Generator
switch |
| 17h |
Reserved |
| 18h |
Detect CPU
information including brand, SMI type (Cyrix or Intel)
and CPU level (586 or 686) |
| 19h |
Reserved |
| 1Ah |
Reserved |
| 1Bh |
Initial interrupts
vector table. If no special specified, all H/W
interrupts are directed to SPURIOUS_INT_HDLR & S/W
interrupts to SPURIOUS_soft_HDLR |
| 1Ch |
Reserved |
| 1Dh |
Initial EARLY_PM_INIT
switch |
| 1Eh |
Reserved |
| 1Fh |
Load keyboard
matrix (notebook platform) |
| 20h |
Reserved |
| 21h |
HPM initialization
(notebook platform) |
| 22h |
Reserved |
| 23h |
Check validity
of RTC value; Load CMOS settings into BIOS stack.
If CMOS checksum fails, use default value instead; Prepare
BIOS resource map for PCI & PnP use. If ESCD
is valid, take into consideration of the ESCD's legacy
information; Onboard clock generator initialization.
Disable respective clock resource to empty PCI &
DIMM slots; Early PCI initialization - Enumerate PCI
bus number, assign memory & I/O resource, search
for a valid VGA device & VGA BIOS, and put it into
C000:0 |
| 24h |
Reserved |
| 25h |
Reserved |
| 26h |
Reserved |
| 27h |
Initialize
INT 09 buffer |
| 28h |
Reserved |
| 29h |
Program CPU
internal MTRR (P6 & PII) for 0-640K memory address;
Initialize the APIC for Pentium class CPU; Program early
chipset according to CMOS setup; Measure CPU speed;
Invoke video BIOS |
| 2Ah |
Reserved |
| 2Bh |
Reserved |
| 2Ch |
Reserved |
| 2Dh |
Initialize
multilanguage; Put information on screen display, including
Award title, CPU type, CPU speed, etc... |
| 2Eh |
Reserved |
| 2Fh |
Reserved |
| 30h |
Reserved |
| 31h |
Reserved |
| 32h |
Reserved |
| 33h |
Reset keyboard
except Winbond 977 series Super I/O chips |
| 34h |
Reserved |
| 35h |
Reserved |
| 36h |
Reserved |
| 37h |
Reserved |
| 38h |
Reserved |
| 39h |
Reserved |
| 3Ah |
Reserved |
| 3Bh |
Reserved |
| 3Ch |
Test 8254 |
| 3Dh |
Reserved |
| 3Eh |
Test 8259
interrupt mask bits for channel 1 |
| 3Fh |
Reserved |
| 40h |
Test 9259
interrupt mask bits for channel 2 |
| 41h |
Reserved |
| 42h |
Reserved |
| 43h |
Test 8259
functionality |
| 44h |
Reserved |
| 45h |
Reserved |
| 46h |
Reserved |
| 47h |
Initialize
EISA slot |
| 48h |
Reserved |
| 49h |
Calculate
total memory by testing the last double last word of
each 64K page; Program writes allocation for AMD K5
CPU |
| 4Ah |
Reserved |
| 4Bh |
Reserved |
| 4Ch |
Reserved |
| 4Dh |
Reserved |
| 4Eh |
Program MTRR
of M1 CPU; initialize L2 cache for P6 class CPU &
program cacheable range; Initialize the APIC for P6
class CPU; On MP platform, adjust the cacheable range
to smaller one in case the cacheable ranges between
each CPU are not identical |
| 4Fh |
reserved |
| 50h |
Initialize
USB |
| 51h |
Reserved |
| 52h |
Test all
memory (clear all extended memory to 0) |
| 53h |
Reserved |
| 54h |
Reserved |
| 55h |
Display number
of processors (multi-processor platform) |
| 56h |
Reserved |
| 57h |
Display PnP
logo; Early ISA PnP initialization and assign CSN to
every ISA PnP device |
| 58h |
Reserved |
| 59h |
Initialize
the combined Trend Anti-Virus code |
| 5Ah |
Reserved |
| 5Bh |
Show message
for entering AWDFLASH.EXE from FDD (optional feature) |
| 5Ch |
Reserved |
| 5Dh |
Initialize
Init_Onboard_Super_IO switch; Initialize Init_Onboard_AUDIO
switch |
| 5Eh |
Reserved |
| 5Fh |
Reserved |
| 60h |
Okay to enter
Setup utility |
| 61h |
Reserved |
| 62h |
Reserved |
| 63h |
Reserved |
| 64h |
Reserved |
| 65h |
Initialize
PS/2 mouse |
| 66h |
Reserved |
| 67h |
Prepare memory
size information for function call: INT 15h ax=E820h |
| 68h |
Reserved |
| 69h |
Turn on L2
cache |
| 6Ah |
Reserved |
| 6Bh |
Program chipset
registers according to items described in Setup &
Auto-Configuration table |
| 6Ch |
Reserved |
| 6Dh |
Assign resources
to all ISA PnP devices; Auto assign ports to onboard
COM ports if the corresponding item in Setup is set
to "AUTO" |
| 6Eh |
Reserved |
| 6Fh |
Initialize
floppy controller; Setup floppy related fields in 40:hardware |
| 70h |
Reserved |
| 71h |
Reserved |
| 72h |
Reserved |
| 73h |
Enter AWDFLASH.EXE
if: AWDFLASH.EXE is found in floppy dive and ALT+F2
is pressed |
| 74h |
Reserved |
| 75h |
Detect and
install all IDE devices: HDD, LS120, ZIP, CDROM... |
| 76h |
Reserved |
| 77h |
Detect serial
ports and parallel ports |
| 78h |
Reserved |
| 79h |
Reserved |
| 7Ah |
Detect and
install coprocessor |
| 7Bh |
Reserved |
| 7Ch |
Reserved |
| 7Dh |
Reserved |
| 7Eh |
Reserved |
| 7Fh |
Switch back
to text mode if full screen logo is supported: if errors
occur, report errors & wait for keys, if no errors
occur or F1 key is pressed continue - Clear EPA or customization
logo |
| 80h |
Reserved |
| 81h |
Reserved |
| 82H |
Call chipset
power management hook: Recover the text fond used by
EPA logo (not for full screen logo), If password is
set, ask for password |
| 83H |
Save all
data in stack back to CMOS |
| 84h |
Initialize
ISA PnP boot devices |
| 85h |
Final USB
initialization; NET PC: Build SYSID structure; Switch
screen back to text mode; Set up ACPI table at top of
memory; Invoke ISA adapter ROM's; Assign IRQ's to PCI
devices; Initialize APM; Clear noise of IRQ's |
| 86h |
Reserved |
| 87h |
Reserved |
| 88h |
Reserved |
| 89h |
Reserved |
| 90h |
Reserved |
| 91h |
Reserved |
| 92h |
Reserved |
| 93h |
Read HDD
boot sector information for Trend Anti-Virus code |
| 94h |
Enable L2
cache; Program boot up speed; Chipset final initialization;
Power management final initialization; Clear screen
and display summary table; Program K^ write allocation;
Program P6 class write combining |
| 95h |
Program daylight
saving; Update keyboard LED and typematic rate |
| 96h |
Build MP
table; Build and update ESCD; Set CMOS century to 20h
or 19h; Load CMOS time into DOS timer tick; Build MSIRQ
routing table |
| FFh |
Boot attempt
(INT 19h) |
